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<p>Chip-specific system clock manager configuration.  
<a href="#details">More...</a></p>

<p><a href="conf__clock_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="define-members"></a>
Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#a7bb6bbe88b7fb398ef8f0befe936e0e7">CONFIG_SYSCLK_SOURCE</a>&#160;&#160;&#160;SYSCLK_SRC_PLL0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#af8bcf7e1ee2ebd2829ebc31be507c6da">CONFIG_SYSCLK_CPU_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#aa952d8094a06be420e244e68286c2dbf">CONFIG_SYSCLK_PBA_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#a50962c914daa31fbc279cd4bccf66f98">CONFIG_SYSCLK_PBB_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#aa31e8248ac7b461b19f7ec827674d16c">CONFIG_SYSCLK_PBC_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga2ea7011abd3d43ef751313c6fc8c2068">CONFIG_USBCLK_SOURCE</a>&#160;&#160;&#160;USBCLK_SRC_PLL0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration symbol for the USB generic clock source.  <a href="group__sysclk__group.html#ga2ea7011abd3d43ef751313c6fc8c2068"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gac73a11432c1931f5f2daa030eda13923">CONFIG_USBCLK_DIV</a>&#160;&#160;&#160;1</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration symbol for the USB generic clock divider setting.  <a href="group__sysclk__group.html#gac73a11432c1931f5f2daa030eda13923"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#a6ea6cd6d377a0bdc9eb60d33e21ee753">CONFIG_PLL0_SOURCE</a>&#160;&#160;&#160;PLL_SRC_OSC0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#a2ecc163c99e6ea17af400470b9497a56">CONFIG_PLL0_MUL</a>&#160;&#160;&#160;(48000000UL / BOARD_OSC0_HZ)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#a382b7ad4d7cc07292d508b8fd28876ba">CONFIG_PLL0_DIV</a>&#160;&#160;&#160;1</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#ac0ab54e87a33e7678bea1402d7ac94ac">CONFIG_PLL1_MUL</a>&#160;&#160;&#160;(48000000UL / BOARD_OSC0_HZ)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__clock_8h.html#ae2b12c38962e21d330d2d1016c88078e">CONFIG_PLL1_DIV</a>&#160;&#160;&#160;1</td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<div class="textblock"><p>Chip-specific system clock manager configuration. </p>
<p>Copyright (C) 2011 Atmel Corporation. All rights reserved. </p>
</div><hr/><h2>Define Documentation</h2>
<a class="anchor" id="a382b7ad4d7cc07292d508b8fd28876ba"></a><!-- doxytag: member="conf_clock.h::CONFIG_PLL0_DIV" ref="a382b7ad4d7cc07292d508b8fd28876ba" args="" -->
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          <td class="memname">#define CONFIG_PLL0_DIV&#160;&#160;&#160;1</td>
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<a class="anchor" id="a2ecc163c99e6ea17af400470b9497a56"></a><!-- doxytag: member="conf_clock.h::CONFIG_PLL0_MUL" ref="a2ecc163c99e6ea17af400470b9497a56" args="" -->
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          <td class="memname">#define CONFIG_PLL0_MUL&#160;&#160;&#160;(48000000UL / BOARD_OSC0_HZ)</td>
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</div>
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<a class="anchor" id="a6ea6cd6d377a0bdc9eb60d33e21ee753"></a><!-- doxytag: member="conf_clock.h::CONFIG_PLL0_SOURCE" ref="a6ea6cd6d377a0bdc9eb60d33e21ee753" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define CONFIG_PLL0_SOURCE&#160;&#160;&#160;PLL_SRC_OSC0</td>
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<a class="anchor" id="ae2b12c38962e21d330d2d1016c88078e"></a><!-- doxytag: member="conf_clock.h::CONFIG_PLL1_DIV" ref="ae2b12c38962e21d330d2d1016c88078e" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define CONFIG_PLL1_DIV&#160;&#160;&#160;1</td>
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</div>
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<a class="anchor" id="ac0ab54e87a33e7678bea1402d7ac94ac"></a><!-- doxytag: member="conf_clock.h::CONFIG_PLL1_MUL" ref="ac0ab54e87a33e7678bea1402d7ac94ac" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define CONFIG_PLL1_MUL&#160;&#160;&#160;(48000000UL / BOARD_OSC0_HZ)</td>
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</div>
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</div>
</div>
<a class="anchor" id="af8bcf7e1ee2ebd2829ebc31be507c6da"></a><!-- doxytag: member="conf_clock.h::CONFIG_SYSCLK_CPU_DIV" ref="af8bcf7e1ee2ebd2829ebc31be507c6da" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define CONFIG_SYSCLK_CPU_DIV&#160;&#160;&#160;0</td>
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<a class="anchor" id="aa952d8094a06be420e244e68286c2dbf"></a><!-- doxytag: member="conf_clock.h::CONFIG_SYSCLK_PBA_DIV" ref="aa952d8094a06be420e244e68286c2dbf" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define CONFIG_SYSCLK_PBA_DIV&#160;&#160;&#160;0</td>
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</div>
</div>
<a class="anchor" id="a50962c914daa31fbc279cd4bccf66f98"></a><!-- doxytag: member="conf_clock.h::CONFIG_SYSCLK_PBB_DIV" ref="a50962c914daa31fbc279cd4bccf66f98" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define CONFIG_SYSCLK_PBB_DIV&#160;&#160;&#160;0</td>
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<a class="anchor" id="aa31e8248ac7b461b19f7ec827674d16c"></a><!-- doxytag: member="conf_clock.h::CONFIG_SYSCLK_PBC_DIV" ref="aa31e8248ac7b461b19f7ec827674d16c" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define CONFIG_SYSCLK_PBC_DIV&#160;&#160;&#160;0</td>
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<a class="anchor" id="a7bb6bbe88b7fb398ef8f0befe936e0e7"></a><!-- doxytag: member="conf_clock.h::CONFIG_SYSCLK_SOURCE" ref="a7bb6bbe88b7fb398ef8f0befe936e0e7" args="" -->
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<div class="memproto">
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          <td class="memname">#define CONFIG_SYSCLK_SOURCE&#160;&#160;&#160;SYSCLK_SRC_PLL0</td>
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